E.09Trace Delay and Length Matching

Enter the trace lengths to calculate delay, skew and the length tolerance that fits your timing budget.

Layer

For stripline, εeff = εr.

For microstrip εeff < εr; you can take it from the E.05 Impedance Calculator.

Depends on the interface budget; e.g. typically 1–5 ps within a differential pair.

Results

Skew (B − A)
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Delay per length
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Trace A delay
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Trace B delay
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Allowed length mismatch
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Status
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    Formulas

    Delay per length
    t_pd = √εeff / c (c = 299.79 mm/ns)
    Skew
    Δt = (L_B − L_A) · t_pd
    Length tolerance
    ΔL_max = Δt_max / t_pd

    How to use

    In high-speed interfaces (DDR, PCIe, USB, Ethernet, JESD204) signals must reach the receiver at the same time. This tool gives the time difference between two traces and the length mismatch corresponding to the interface’s timing budget. Signals travel more slowly on inner layers (stripline) than on outer layers (microstrip); for traces that change layers, calculate the delay for each layer separately.

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