E.06Phase Noise → Jitter

Enter phase noise values from the datasheet to calculate jitter and the ADC SNR limit.

12 kHz – 20 MHz is the band commonly used for communication clocks.

Results

RMS jitter
—
Integrated phase noise
—
RMS phase error
—
ADC SNR limit
—
Band used
—

    Formulas

    Between points
    L(f) linear on log-log axes (dB/decade)
    RMS phase error
    σφ = √(2 · ∫ 10^(L(f)/10) df) [rad]
    RMS jitter
    σt = σφ / (2π · f₀)
    Jitter-limited SNR
    SNR = −20 · log₁₀(2π · f_in · σt)

    Why it matters

    In high-speed ADCs, sampling clock jitter directly limits SNR as input frequency rises. For example, 100 fs of jitter at a 100 MHz input limits SNR to about 84 dB, meaning resolution beyond about 14 bits cannot be used.

    Empty measurement points are ignored. The result assumes the curve is linear (log-log) between the given points; spurs are not included.

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